Bonfring International Journal of Power Systems and Integrated Circuits
Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year
Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)
High Efficiency SEPIC PFC Interleaved Converter with Reduced Ripple Factor
M.C. Bini and S. Chinnaiya
Abstract:
This paper presents an interleaving SEPIC power factor correction converter can operate as a power supply with reduced ripple factor and improved power factor with dual feedback control loops while it preserves the cost and size. Compared with the conventional capacitive idling SEPIC PFC Converter, the proposed converter demonstrates much improved current handling capability with reduced current and voltage ripples. The proposed design presents an isolated interleaved DC-DC converter, which features the decoupling of pre-stage and second-stage feedback loops while preserves the cost, size and simplicity of the conventional SEPIC PFC converter. The interleaved technique is used to reduce the ripple factor of the output voltage. The degree of control introduced here can easily achieve a sinusoidal input current at near unity power factor and maintain constant output dc voltage respectively. The reference voltage of the energy transfer capacitor is always slightly higher than the AC input voltage peak value, which reduces the loss of the pre-stage PFC converter and improves the overall efficiency of converter. Analysis and simulation results of the interleaving SEPIC PFC converter have been presented. The proposed converter shows improved load capacity, reduced ripple factor and higher efficiency over the existing converters.
Keywords: Interleaved SEPIC Converter, Power Factor Correction, Ripple Factor Reduction
Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development
Pages: 31-34
Issue Date: February , 2012
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