Implementation of Parallel DA Technique for DWT-IDWT on FPGA for Image Compression
Abstract
Due to the increasing traffic caused by multimedia information and digitized form of representation of images, image compression become a necessity. The Parallel Distributive Arithmetic (DA) architecture has a reduced latency and a good throughput. This design is twice faster than the simple Distributive Arithmetic Architecture and is thus suitable for applications that require high speed image processing algorithms.
Keywords Discrete Wavelet Transform (DWT), Distributive Arithmetic (DA), Look-Up Table (LUT), FIR Filter