Bonfring International Journal of Research in Communication Engineering
Online ISSN: 2277-5080 | Print ISSN: 2250-110X | Frequency: 4 Issues/Year
Impact Factor: 0.528 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)
Design of High Gain two Stage Amplifier for ADC Applications Using Cadence 180nm Technology
Abstract:
In this paper a two stage CMOS compensated op-amp and its analysis is presented. In order to obtain a high dc gain, a two stage CMOS op-amp is used. The two stage op-amp consists of a op-amp as current source load using common source designed in the first stage and a common source output Beta multiplier and start up circuit stage in the second stage .In addition to the dc gain, the main advantage of this op-amp is the voltage swing .The simulated results shows a DC gain of 82dB , and it has drain current 68 μA phase margin of 585,ICMR of 785mV to 1.85V .The total power dissipation obtained from the op-amp circuit is 0.4 mW. For comparison, a similar op-amp which uses a double cascade telescopic input has been realized .And both these op-amps are designed using 180nm CMOS process.
Keywords: Cascaded OP-AMP, CMOS Technology, CMRR, Startup and Beta Multiplier OP-AMP, High Gain, 180nm Technology
Volume: 6 | Issue: Special Issue on Recent Advancements in Electronics and Communication Engineering|Editors:Dr.G.A. Bidkar,Dr.C. Vijaya and Dr.S.B. Kulkarni
Pages: 124-130
Issue Date: November , 2016
DOI: 10.9756/BIJRCE.8217
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